1. Field of the Invention
The present invention relates to a wiring layout to weaken an electric field generated between the lines exposed to a high voltage, particularly to the bit lines of a nonvolatile semiconductor memory.
2. Description of the Related Art
First of all, the prior art of the present invention will be explained taking a NAND flash memory, a kind of nonvolatile semiconductor memory, as an example.
FIG. 1 shows an example of a cell array of a NAND flash memory. In this example, only one NAND block (erase unit) is shown to simplify the explanation.
A NAND flash memory is a kind of electrically rewritable nonvolatile semiconductor memory. A NAND block represents an erase unit, and all the data in the memory cell of a NAND block is erased simultaneously. A NAND block has a plurality of NAND cell units 1. These NAND cell units 1 are placed in a cell""s P-well area, CPWELL, for example.
A NAND cell unit comprises a NAND string comprising a plurality of memory cells 2 connected in series, one select gate transistor 3 connected to one end of the NAND series, and another select gate transistor 3 connected to another end of the NAND series. The one select gate transistor 3 connected to the one end of the NAND series is connected to a common source line CELSRC, and the another select gate transistor 3 connected to the another end of the NAND series is connected to bit lines BL1exe2x80x94BLne and BL1oxe2x80x94BLno.
Word lines WL 0, WL 1 to WL 15 are connected to the memory cells 2 in the NAND cell unit, and they function as control gate electrodes of the memory cells 2. Select gate lines SGS and SGD are connected to the select gate transistors 3 in the NAND cell unit 1, and they function as gate electrodes of the select gate transistors 3.
In this example, a sense amplifier (S/A) 4 employs a cell array structure with two bit lines BLie and BLio (i=1, 2, to n) connected through a select circuit 5A. Two bit lines BLie and BLio are connected to a shielded power line BLSHIELD through a select circuit 5B. With this structure, a so-called shielded bit line reading method can be used upon reading operation.
Namely, since the N-channel MOS transistor 6A turns on when the control signal BLSe is xe2x80x9cHxe2x80x9d and the control signal BLSo is xe2x80x9cLxe2x80x9d, the even-numbered bit line BLie is electrically connected to the sense amplifier 4. As the control signal BIASe becomes xe2x80x9cLxe2x80x9d and the control signal BIASo becomes xe2x80x9cHxe2x80x9d at this time, the N-channel MOS transistor 7B is ON and the shielding potential VSHIELD (e.g., 0V) is supplied to the odd-numbered bit line BLio.
Further, since the N-channel MOS transistor 7A turns on when the control signal BLSe is xe2x80x9cLxe2x80x9d and the control signal BLSO is xe2x80x9cHxe2x80x9d, the odd-numbered bit line BLio is electrically connected to the sense amplifier 4. As the control signal BIASe becomes xe2x80x9cHxe2x80x9d and the control signal BIASo becomes xe2x80x9cLxe2x80x9d at this time, the N-channel MOS transistor 6B is ON and the shielding potential VSHIELD (e.g., 0V) is supplied to the even-numbered bit line BLie.
It is noted here that the even and odd numbers are determined by the bit line numbers counted from left to right assuming the leftmost bit line to be 0.
Since all bit lines BL1e, . . . BLne; BL1o, . . . BLno become high potential (erase potential) upon erasing, the N-channel MOS transistors 6A, 6B and 7A, 7B in the select circuits 5A and 5B, respectively, consist of high voltage MOS transistors.
In a NAND flash memory, during writing and erasing, electric charge is injected into/ejected from the floating gate electrode by an FN tunnel current.
During the writing operation, 20V is applied to the selected word line WLj and 0V is applied to the cell""s P-well area (the memory cell channel) CPWELL, for example.
During the erasing operation, 0V is applied to the word line WL0, WL1 to WL15 in the selected NAND block, and 20V is applied to the cell""s P-well area (channel of memory cell) CPWELL, for example.
When erasing, all bit lines BL1exe2x80x94BLne and BL1oxe2x80x94BLno are actually floating.
However, when 20V is applied to the cell""s P-well area CPWELL, a forward bias diode (cell""s P-well area+N-type diffusion layer) is connected between the cell""s P-well area CPWELL and the bit lines BL1exe2x80x94BLne and BL1oxe2x80x94BLno. As a result, the bit lines BL1exe2x80x94BLne and BL1oxe2x80x94BLno are also charged to about 20V.
As described above, during writing or erasing, the selected word line WLj or all the bit lines BL1exe2x80x94BLne and BL10xe2x80x94BLno are charged to about 20V. Therefore, as a potential difference between these lines and other lines increases, a dielectric breakdown occurs between these lines, and a line short-circuit problem arises.
Particularly, in recent years, the cell array has become finer and the wiring design rule has become narrower. This increases the possibility of short-circuit due to an intense electric field in and in the proximity of a cell array.
Hereinafter, the problem will be discussed in detail taking bit lines of a nonvolatile semiconductor memory, as an example.
FIG. 2 shows a wiring layout of the part indicated as the area B in FIG. 1. FIG. 3 shows an equivalent circuit diagram of the layout of FIG. 2.
The bit lines BL1e, BL1o, BL2e, BL2o are arranged as metal lines M1 with minimum width and minimum space in a memory chip.
The above-mentioned minimum width means the minimum width determined by the processing technique of lithography. The minimum space means the minimum space S1 which is influenced by the lithography technique, but in principle makes no short-circuit in the lines due to dielectric breakdown when a voltage (potential difference) V1 is generated between the lines.
The bit lines BL1e and BL2e are connected to the N-type drain diffusion layer of the N-channel MOS transistor 6B through the V1 contact plug, metal line M0 and CS contact plug. The bit lines BL1o and BL2o are connected to the N-type drain diffusion layer of the N-channel MOS transistor 7B through the V1 contact plug, metal line M0 and CS contact plug.
The shielded power line BLSHIELD is connected to the N-type source diffusion layers of N-channel MOS transistors 6B and 7B through a V1 contact plug, a metal line M0 and a CS contact plug.
The metal line M0 means the lines in the lowest layer which are directly connected to a silicon substrate (e.g., a N-type diffusion layer) Si using a CS contact plug without passing through other metal lines. The metal line M1 means the lines in one layer above M0.
The gate electrodes of the N-channel MOS transistors 6B and 7B are made of conductive polysilicon film containing impurities, for example.
In the wiring layout of this example, since the bit lines BL1e, BL1o, BL2e, BL2o are arranged with minimum width and minimum space, a fringe is not given to the bit lines BL1e, BL1o, BL2e, BL2o in the contact area (above the V1 contact plug). Further, the size of the V1 contact plug is larger than the width of the bit lines BL1e, BL1o, BL2e, BL2o.
Therefore, the space between the bit lines BL1e, BL1o, BL2e, BL2o and the V1 contact plug becomes smaller than the minimum space where no dielectric breakdown occurs between the lines.
Specifically, in the example shown in FIGS. 2 and 3, the space between the bit line BL1o and the V1 contact plug in the area X1 becomes smaller than the minimum space. The space between the shielded power line BLSHIELD and the V1 contact plug in the area X2 is also reduced to be smaller than the minimum space.
As a result, an electric field concentrates on these reduced areas, and a dielectric breakdown occurs, spoiling the reliability of the nonvolatile semiconductor memory.
Further, in the wiring layout of this example, the bit lines BL1e, BL1o, BL2e, BL2o are arranged with minimum width and minimum space, and the space between the shielded power supply BLSHIELD and the bit lines BL1e, BL1o, BL2e, BL2o is set to be minimum.
However, it is to be noted that this minimum space is determined by the voltage V1 impressed across the bit lines BL1e, BL1o, BL2e, BL2o. Namely, a voltage larger than V1 may be applied to between the shielded power line BLSHIELD and the bit lines BL1e, BL1o, BL2e, BL2o.
In this case, a line short-circuit occurs due to concentration of electric field between the shielded power line BLSHIELD and the bit lines BL1e, BL1o, BL2e, BL2o, failing to ensure the reliability of the nonvolatile semiconductor memory.
FIG. 4 shows signal waveforms upon erasing.
At the time t1 to t3, 20V is applied as an erasing voltage to the cell""s P-well area CPWELL. The bit lines BL1e, BL1o, BL2e, BL2o are charged to about 20V, specifically 20Vxe2x80x94Vf. (Vf is the forward bias voltage between the cell""s P-well area and N-type diffusion layer.) The shielded power line BLSHIELD is charged to Vcc (approx. 3V, for example).
Therefore, during the erase operation, a potential difference of 20Vxe2x80x94Vcc occurs between the bit line BL1o and the shielded power line BLSHIELD in FIG. 2, for example.
Particularly, in the areas X1 and X2, the space between the bit line BL1o and the shielded power line BLSHIELD is narrower than the minimum space. Further, considering contact holes, line shifts or uneven shapes occurred during the lithography, the space between the bit line BL1o and the shielded power line BLSHIELD may be reduced further.
Therefore, there is a very large possibility of line short-circuit due to concentration of electric field on the area between the shielded power line BLSHIELD and the bit lines BL1e, BL1o, BL2e, BL2o.
A short-circuit in a line causes leakage of the electric charge on erasing from the cell""s P-well area to the bit line BL1o, for example and further to the shielded power line BLSHIELD, failing to supply the cell""s P-well area with the voltage large enough to do the erase operation.
This will result in defective erasing, lowering the reliability of the nonvolatile semiconductor memory.
As explained above, as the design rule becomes very small with the finer element, the possibility of a short-circuit between the lines exposed to high voltage increases. This has been the problem in the prior art.
A semiconductor device according to a first aspect of the present invention comprises first and second lines arranged with a first interval, and third and fourth lines arranged with a second interval wider than the first internal; wherein the first internal is a minimum interval less than 0.12 xcexcm, and a maximum value of a voltage generated between the third and fourth lines is greater than a maximum value of a voltage generated the first and second lines.
A semiconductor device according to a second aspect of the present invention comprises first and second lines in a wiring layer arranged with a first interval, a third line arranged in the wiring layer, wherein a second interval between the first and third lines is wider than the first interval, and a first transistor configured to connect the second and third lines; wherein the first interval is a minimum interval less than 0.12 xcexcm, and a maximum value of a voltage generated between the first and third lines is greater than a maximum value of a voltage generated between the first and second lines.
A semiconductor device according to a third aspect of the present invention comprises first and second lines in a wiring layer arranged with a first interval, a third line arranged in the wiring layer, and a first transistor configured to connect the second and third lines; wherein the first interval is a minimum interval less than 0.12 xcexcm, and a maximum value of a voltage generated between the first and third lines is greater than a maximum value of a voltage generated the first and second lines, and the third line is arranged at a position not adjacent to the first line.